2/1/2019 8:42:48 PM


  • Keynote 1

 Wireless Evolution Towards 5G and Beyond

Fumiyuki Adachi

Research Organization of Electrical Communication, Tohoku University, Japan



Mobile communications network has now evolved into the 4th generation (4G). An increasing popularity of broadband services demands a significant improvement in the spectrum efficiency and energy efficiency. Promising approach is to enhance the radio access network by using MIMO technology. After briefly overviewing the evolution of mobile communications network, we will overview the recent advances in distributed MIMO RAN. A number of distributed antennas are deployed over a traditional macro-cell area covered by a macro-cell base station (MBS). They are connected to the MBS by the optical mobile fronthaul. Distributed MIMO RAN exploits the spatial distribution of both antennas and users. Some of distributed antennas near a user terminal are selected to perform distributed MIMO cooperative transmission. A new frequency band, e.g. the mm wave band, where abundant bandwidth remains unused, will be utilized. Therefore, there exists high Doppler shift, which cases the channel estimation problem. Furthermore, adjacent macro-cells are loosely connected, and hence, the inter-cell interference (ICI) problem will be produced. In this talk, we will present adaptive channel estimation and adaptive ICI coordination (ICIC). Finally, we will discuss about RAN evolution into beyond 5G.


Fumiyuki Adachi received the B.S. and Dr. Eng. degrees in electrical engineering from Tohoku University, Sendai, Japan, in 1973 and 1984, respectively. In April 1973, he joined the Electrical Communications Laboratories of Nippon Telegraph & Telephone Corporation (now NTT) and conducted various researches on digital cellular mobile communications. From July 1992 to December 1999, he was with NTT Mobile Communications Network, Inc. (now NTT DoCoMo, Inc.), where he led a research group on Wideband CDMA for 3G systems. Since January 2000, he has been with Tohoku University, Sendai, Japan. His research interests are in the area of wireless signal processing (multi-access, equalization, antenna diversity, adaptive transmission, channel coding, etc.) and networking.

He is an IEEE Life Fellow and an IEICE Fellow. He was a recipient of the IEEE Vehicular Technology Society Avant Garde Award 2000, IEICE Achievement Award 2002, Thomson Scientific Research Front Award 2004, Ericsson Telecommunications Award 2008, Prime Minister Invention Award 2010, KDDI Foundation Excellent Research Award 2012, C&C Prize 2014, IEEE VTS Stuart Meyer Memorial Award 2017, and IEEE ComSoc RCC Technical Recognition Award 2017. He is listed in Highly Cited Researchers 2001 (


  • Keynote 2

 Embedding Strategic Intelligence in Wireless Communications and Sensing Systems

Sangarapillai Lambotharan

Loughborough University, UK



With the development of the Internet of Things and an abundance of sensors, it is expected that the number of connected devices will reach 50 billion globally by 2020. All these devices will need to operate in a radio congested environment and will compete for the scarce frequency spectrum. This competition for resources between fixed and mobile users presents major challenges to future generation wireless systems and needs a mathematical framework for its solution.  Likewise, in emergent wireless networks and sensor systems, there is competitive demand for higher data rates, efficient spectrum utilization and autonomous operation.

The talk presents the successful application of game theoretic methods in economics, political science and evolutionary biology, to embed strategic operation in such wireless communications and sensing systems. In particular, the focus will be on the application of these methods to enable wireless and sensor systems to adapt to changes in their environment, optimise operational parameters in a distributed manner and interact strategically to mitigate disturbances caused by malicious transmitters. The talk will be concluded by presenting a collection of current and future application scenarios including 5G networks, distributed radars, smart grids and data mining.


Sangarapillai Lambotharan is Professor of Digital Communications and the Head of Signal Processing and Networks Research Group at Loughborough University, UK.  He received his PhD degree in Digital Signal Processing from Imperial College London, UK in 1997. His previous appointments include Visiting Scientist at Cornell University, Lecturer at King’s College London, Senior Lecturer at Cardiff University and Research Engineer at Motorola. He has published more than 200 technical journal and conference articles in signal processing for communications, in particular on mathematical optimizations for cognitive radio and MIMO networks. He is a member of the editorial board of IET Signal Processing.  His current research interests include massive MIMO, radars, data mining, smart grids, machine learning, game theory and convex optimizations. He is a Senior Member of IEEE and a Fellow of IET.


  • Keynote 3

 Energy-Quality Scalable Integrated Systems - Preserving Energy

Downscaling in the Decade Ahead

Massimo Alioto

ECE - National University of Singapore




The historical 100X/decade energy down-scaling is currently being threatened by the end of Moore’s law, and the limited prospective energy gains from approaches that have been already exploited extensively (e.g., heterogeneous systems, ultra-low voltage, parallelism). Major shifts from traditional sensing/processing paradigms are now mandatory, and new design dimensions and tradeoffs that enable further energy reductions need to be explored.

In this talk, energy-quality (EQ) scalable circuits and systems are introduced as a viable direction to continue the historical exponential energy down-scaling. EQ-scalable systems dynamically and explicitly trade off energy and quality from sensor to circuit, architecture, algorithm, and up to system level. Recent and novel approaches are discussed to minimize the energy at run time, based on the actual quality target that is set by the specific task, the context, and the specific dataset at hand. In this talk, quality is treated as an explicit knob, eliminating the quality slack that is traditionally imposed by worst-case design across different applications, contexts, datasets, and the pessimistic design margin to counteract process/voltage/temperature variations. Interesting convergence with machine learning and other important applications is discussed to provide an insight into the inter-dependence of algorithms, architectures and circuits. Several silicon demonstrations are illustrated to quantify the benefits offered by energy-quality scaling, and to identify the challenges that need to be solved to fulfill its potential.


Massimo Alioto is Associate Professor at the ECE Department of the National University of Singapore, where he leads the Green IC group and the Integrated Circuits and Embedded Systems area. Previously, he held positions at the University of Siena, Intel Labs – CRL (2013), University of Michigan - Ann Arbor (2011-2012), University of California – Berkeley (2009-2011), EPFL - Lausanne.

He is (co)author of 250+ publications on journals and conference proceedings, and three books with Springer. His primary research interests include ultra-low power VLSI circuits and systems, self-powered systems, near-threshold circuits for green computing, widely energy-scalable integrated systems, hardware security, and circuit techniques for emerging technologies.

He is the Editor in Chief of the IEEE Transactions on VLSI Systems (2019-2020), and Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2018). Prof. Alioto was the Chair of the “VLSI Systems and Applications” Technical Committee of the IEEE CASS (2010-2012), Distinguished Lecturer (2009-2010), and members of the Board of Governors (2015-2020). He served as Guest Editor of numerous journal special issues, Technical Program Chair of several IEEE conferences (ISCAS 2022, SOCC, PRIME, ICECS, VARI, NEWCAS, ICM), and TPC member (ISSCC, ASSCC). Prof. Alioto is an IEEE Fellow.

  • Keynote 4

 Integrated Magnetic Probe and Application for Device Diagnosis

Kunihiro Asada

VLSI Design and Education Center (VDEC), University of Tokyo, Japan




The spatial resolution of coil-based magnetic probe is determined by the coil size. A smaller coil has a higher spatial resolution but a weaker level of output signal, which results in a worse signal-to-noise (S/N) ratio. A solution of this trade-off problem is integration of a small coil with a low-noise amplifier on a semiconductor chip. In this presentation, firstly, structures and fabrication procedure of our integrated magnetic probes will be introduced along with their characteristics. Next, an estimation method of current distribution from measurement data of the magnetic probe is introduced, as a theoretical basis of the integrated magnetic probe application. It is a reverse modeling from magnetic field data to current distribution in circuit. Though it is a straightforward procedure to calculate magnetic field based on a known current distribution in general, a practical problem is the existence of noise. Here a method to estimate most-likely current distribution from magnetic field with random noise will be introduced under the constraint of KCL. Finally, two examples of application will be shown. The first example is measurement results of gate leak current in power devices (IGBT), where the location of the leakage has been successfully detected based on “valley detection method” with a good agreement of a microscopic device diagnosis. The second example is an analysis of power network integrity of LSI. By comparing a normal chip with an abnormal chip with missing VIAs in power network, the magnetic probe has successfully detected subtle differences in magnetic fields, which has been translated to an abnormal power current map analytically. Both the above examples show that the integrated magnetic probe has a potential to be utilized for improving device reliability and fabrication technologies.


Dr. Kunihiro Asada is Emeritus Professor of the University of Tokyo, Japan. He received the BS, MS and PhD from the University of Tokyo in 1975, 1977 and 1980, respectively. In 1980 he joined the Faculty of Engineering, the University of Tokyo. From 1985 to 1986 he stayed at Edinburgh University as a visiting scholar. From 1990 to 1992 he served as the editor of IEICE Transactions on Electronics. In 1996 he established VLSI Design and Education Center (VDEC) in the University of Tokyo and served as the Director of VDEC from 2000 to 2018. He also served as the Chair of IEEE/SSCS Japan Chapter in 2001 -2002 and the Chair of IEEE Japan Chapter Operation Committee in 2007-2008. He is currently a managing director of the Takeda Foundation and the Chair of the Young Takeda Award Committee. His research interest is design and analysis of integrated systems and devices. He is a member of IEEE, IEICE and IEEJ.